Back-end Electronics

The Belle DAQ system employs a simple track-and-hold architecture, in which the front-end electronics is temporarily inhibited upon receipt of a level-1 trigger. The time required for the analog multiplexer scan of VA1 outputs determines the readout deadtime. Since the scan rate is 5 MHz and each FADC channel must read 640 VA1 front-end channels, the minimum deadtime is 128 $\mu$s, which is less than the 200 $\mu$s global maximum for Belle. Once all scans are complete and the digital data are buffered in FIFOs, the modules release the busy signal and the system is ready to accept and process another level-1 trigger [22].
This data buffering scheme allows the DSP modules to implement pedestal subtraction and zero suppression, and low-level data formatting asynchronously, so that no additional deadtime is introduced.