FADC system

Figure shows the block diagram of the FADC module, which is called ``Halny''. Each ``Halny'' module incorporates four channels of FADC, FIFO buffering, and Motorola DSP56302 digital signal processor. The DSPs carry out the pedestal subtraction and zero suppression calculations on a channel-by-channel basis and implement low-level data formatting. The DSPs also calculate pedestals and hit thresholds using a dynamic algorithm that automatically adjusts for pedestal shifts and changes in noise level.

Figure: Block diagram of a $Halny$ FADC module.