FASTBUS TDC readout systems

We adopted a charge-to-time (Q-to-T) technique to read out signals from most of the detectors. Instead of using ADC to digitize the amplitude of a signal, the charge is once stored in a capacitor and discharged at a constant rate. Two pulses, the separation of which is proportional to the signal amplitude, are generated at the start and stop times of the discharge. By digitizing the time interval of the two timing pulses with respect to a common stop timing, we can determine both the timing and the amplitude of the input signal. The hold timing is generated either by a self-gate method or the trigger signal from a timing distributer module, TDM. The mechanism is illustrated in Fig. .

Figure: Concept of the Q-to-T and TDC based digitization.

For time digitization, we use a multi-hit FASTBUS TDC module, LeCroy LRS1877S. Up to 16 timing pulses are recorded for 96 channels in a single width module with a sparsification capability. The least significant bit is 500 ps. A programmable time window has a 16-bit range, which corresponds to a full scale of 32 $\mu$s. Most of the detectors, CDC, ACC, TOF, ECL and EFC, are read out by using the Q-to-T and TDC technique. The use of the Q-to-T technique reduces the number of cables for CDC wires into a half. In the case of TOF, the time resolution of 100 ps is achieved by using a time stretcher which expands the pulse width by a factor of 20. In the case of ECL, a 16-bit dynamic range is achieved by using three ranges. A signal is divided and fed into three preamplifiers of different gains, converted to the time pulse and merged with an exclusive- logic circuit. For a small signal, all the three ranges give short pulses and the final output has 4 time pulses. By contrast, for a large signal, high and middle gain pulses overflow and the final output has only 2 time pulses from the low gain range. After digitization, the range is identified by the number of time pulses for the pulse. The KLM strip information is also read out by using the same type of TDC. Strip signals are multiplexed into serial lines and recorded by TDC as the time pulses. These pulses are decoded to reconstruct hit strips. Similarly, a large number of trigger signals including those for the intermediate stages are recorded using TDC. A full set of trigger signals gives us complete information for trigger study. We developed a unified FASTBUS TDC readout subsystem that is applicable to all the detectors except SVD. A FASTBUS processor interface, FPI, developed by us controls these TDC modules, and FPI is controlled by a readout system controller in a master VME crate. Readout software runs on the VxWorks real time operating system on a Motorola 68040 CPU module, MVME162. Data are passed to an event builder transmitter in the same VME crate. A schematic view of the system is shown in Fig. . The overall transfer rate of the subsystem is measured to be about 3.5 MB/sec.

Figure: Schematic view of the FASTBUS TDC readout system.