SVD readout system

SVD data are read out from 81,920 strip channels, whose occupancy is typically a few percent depending on the beam condition. The charge information is read out by intelligent flash ADC modules with an embedded DSP, which performs data sparsification [87]. The resulting data size is 10 to 20 kB, which is larger than the capacity of a single event builder transmitter. The SVD readout system is divided into four VME crates, in each of which signals are read out in the flash ADC modules and transferred to the event builder in parallel. The SVD readout sequence is synchronized from an external control crate which receives the timing signal from the sequence controller. The schematic diagram of the SVD readout system with 4 readout VME crates is shown in Fig. . The readout software for flash ADC is combined with the event builder transmitter software that runs on a SPARC VME CPU. By doing this, the overhead of extra data copying is minimized.

Figure: Schematic view of the SVD readout system with 4 readout VME crates.