Rear-end receiver and digitizer

The receiver receives analog signals through a transformer which cancels a common-mode noise in the twisted-pair cable. After the gain adjustment, the signal is split into two. One is sent to a charge integrator and the other to a sum amplifier which makes an analog sum of preamplifier signals from a trigger cell. The cell is a group of two or four BGO crystals.
The summed signal is sent to a constant-fraction discriminator (CFD) for generating gates for the charge integrator and the trigger. The integrator integrates the analog signal within the gate and produces an ECL signal whose width is proportional to the charge integrated. It is implemented by LeCroy MQT300A chip. The ECL signal is sent through a 30-m long twisted-pair cable to the electronics hut.
The ECL signal goes through a fanout located in the hut, making another copy. One signal is sent to a time-to-digital converter (TDC) for local EFC DAQ. The other is sent to TDC for Belle global DAQ. TDC used is a multi-hit Fastbus TDC of LeCroy 1887S and is operated in a common-stop mode.