Delay and decision logic

Figure shows the TOF trigger decision logic. The TOF detector multiplicity and event topology are calculated in 32 MHz pipelines consisting of Xilinx FPGA chips. The use of FPGAs allows us to change the pipeline logic depending on the running conditions. The multiplicity pipeline calculates the multiplicity of hits for GDL and the multiplicity clusters for SVD where a cluster is formed by adjacent hits. A multiplicity threshold is set independently for GDL and SVD. The topology pipeline is currently designed to trigger events with a back-to-back topology. It can also independently determine the event opening angle. Various pipeline algorithms take typically less than 15 cycles which introduce a 500 ns delay.

The timing signal must be delayed while the event multiplicity and topology are calculated in the pipelines. Furthermore, the delay time should be programmable to allow for different pipeline delays. The timing signal is thus delayed using a FIFO which is also controlled by the 32 MHz RF clock. The delay is set to an integral number of clock cycles when FIFO is initialized. To maintain the $\sim$5 ns timing resolution, the timing signal is converted to a 7 bit signal at the FIFO input, each bit separated by 5ns. The relative delay between the incoming timing signal and the RF clock edge is encoded into 7 bits. A similar decoding is applied at the FIFO output which restores the initial phase to within $\pm$ 2.5 ns.

The timing signal is then combined with the information from the pipelines and sent to GDL and SVD. Currently, to keep the timing signal rate below 70 kHz the timing signal is only given for events in which the multiplicity of hits is greater than or equal to two. This criteria also gives an acceptable rate for SVD.

Figure: TOF trigger delay and decision logic.