GDL

The configuration of GDL is shown in Fig. . GDL receives up to 48 trigger signals from sub-detectors and makes global correlations among them. It generates up to 48 types of event trigger signals. It is designed to function in a pipelined manner with a 32 MHz clock in order to avoid deadtime losses and it takes 350 ns to generate the final trigger signal. The functionality of GDL is shared by several types of modules as shown in Fig. :

• Input Trigger Delay (ITD) which adjusts the timing of input trigger signals to meet the latency of 1.85 $\mu$s,
  
• Final Trigger Decision (FTD) which performs the global trigger logic, correlating the information from sub-detector triggers,
  
• Prescale and Mask (PSNM) which prescales the high rate input triggers for calibration and monitoring purpose and disables the unused triggers from FTD, and
  
• Timing Decision (TMD) which generates the final trigger signal at 2.2 $\mu$s latency based on the timing information of the "timing trigger" from TSC and ECL.

The ITD, FTD, PSNM and TMD modules serve as the components of GDL. They are designed as single width 6U VME modules. These modules extensively use Xilinx FPGA and CPLD chips [84] in order to provide sufficient flexibility in the system.

The timing decision logic uses a 64 MHz clock to provide 16 ns ($\pm$8 ns) timing accuracy. The trigger signals from GDL are synchronized to the beam crossing time since clock signals are made from the KEKB RF signal. The final trigger from GDL provides the timing for ADC gates and TDC stops. The trigger signals at each step of GDL are sent to scalers to monitor rates and deadtimes. They are also fed into FASTBUS multi-hit TDCs (LeCroy 1877S) to record the timing so that the timing and logic of GDL can be verified. The detailed description of the GDL system can be found in Ref.[83].

Figure: Schematic design of GDL.