The total cross sections and trigger rates at the goal luminosity of
cms for various physical processes of interest
are listed in
Table .
We need to accumulate samples of Bhabha and events to
measure the luminosity and to calibrate the detector responses, but,
since their rates are very large, these trigger rates must be
prescaled by a factor 100. Because of their distinct signatures,
this should not be difficult. Although the cross section for physics
events of interest is reasonably small, they can be triggered by
appropriately restrictive conditions.
Because of the high beam current, high beam backgrounds are expected.
Based on simulation studies, we expect 100 Hz from beam-related
backgrounds which are dominated by spent electrons and positrons.
Since the rates are very sensitive to actual accelerator conditions,
it is difficult to make a reliable estimate. Therefore, the trigger
system is required to be robust against unexpectedly high beam
background rates. The trigger conditions should be flexible so that
background rates are kept within the tolerance of the data acquisition
system (max. 500 Hz), while the efficiency for physics events of
interest is kept high. It is important to have redundant triggers to
keep the efficiency high even for varying conditions. The Belle
trigger system has been designed and developed to satisfy these
requirements.
The Belle trigger system consists of the Level-1 hardware trigger and
the Level-3 software trigger. The latter has been designed to be
implemented in the online computer farm.
Fig. shows the schematic view of the Belle
Level-1 trigger system [83]. It consists of the
sub-detector trigger systems and the central trigger system called the
Global Decision Logic (GDL). The sub-detector trigger systems are
based on two categories: track triggers and energy triggers. CDC and
TOF are used to yield trigger signals for charged particles. CDC
provides - and - track trigger signals. The ECL trigger
system provides triggers based on total energy deposit and cluster
counting of crystal hits. These two categories allow sufficient
redundancy. The KLM trigger gives additional information on muons and
the EFC triggers are used for tagging two photon events as well as
Bhabha events. The sub-detectors process event signals in parallel
and provide trigger information to GDL, where all information is
combined to characterize an event type. Information from SVD has not
been implemented in the present trigger arrangement.
Considering the ultimate beam crossing rate of 509 MHz (2 ns interval) with the full bucket operation of KEKB [5], a "fast trigger and gate" scheme is adopted for the Belle trigger and data acquisition system. The trigger system provides the trigger signal with the fixed time of 2.2 s after the event occurrence. The trigger signal is used for the gate signal of the ECL readout and the stop signal of TDC for CDC, providing . Therefore, it is important to have good timing accuracy. The timing of the trigger is primarily determined by the TOF trigger which has the time jitter less than 10 ns. ECL trigger signals are also used as timing signals for events in which the TOF trigger is not available. In order to maintain the 2.2 s latency, each sub-detector trigger signal is required to be available at the GDL input by the maximum latency of 1.85 s. Timing adjustments are done at the input of GDL. As a result, GDL is left with the fixed 350 ns processing time to form the final trigger signal. In the case of the SVD readout the TOF trigger also provides the fast Level-0 trigger signal with a latency of 0.85 s. The Belle trigger system, including most of the sub-detector trigger systems, is operated in a pipelined manner with clocks synchronized to the KEKB accelerator RF signal. The base system clock is 16MHz which is obtained by subdividing 509MHz RF by 32. The higher frequency clocks, 32MHz and 64MHz, are also available for systems requiring fast processing.
The Belle trigger system extensively utilizes programmable logic chips, Xilinx Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD) chips [84], which provide the large flexibility of the trigger logic and reduce the number of types of hardware modules.
Physics process | Cross section (nb) | Rate (Hz) |
(4S) | 1.2 | 12 |
Hadron production from continuum | 2.8 | 28 |
+ | 1.6 | 16 |
Bhabha ( 17) | 44 | 4.4 |
( 17) | 2.4 | 0.24 |
2 processes ( 17, 0.1 GeV/c) | 15 | 35 |
Total | 67 | 96 |